Electronic Design Process Symposium

Keynote

Traditional semiconductor development relies on a rigid, waterfall methodology where architecture, microarchitecture, layout, and physical verification occur in isolated, sequential stages. This linear pipeline creates a compounding penalty: late-stage physical constraints frequently force costly, multi-month iterations back to early architectural phases.

This session presents a shift away from legacy waterfall structures toward a spec-driven development process powered by Artificial Chip Intelligence (ACI®). At the core of this methodology is a physics-informed foundation model that natively encodes downstream physical realities—such as thermal dynamics, parasitics, and manufacturing constraints—directly into the initial specification phase. By embedding these multi-domain physics rules into the model's latent space, the system enables spherical, concurrent optimization. Instead of stepping through isolated design walls, architectural decisions and physical impacts are evaluated simultaneously across all design dimensions at once.

We will demonstrate how this concurrent paradigm eliminates the traditional disconnect between intent and implementation, allowing engineers to operate as high-level system intent directors while the cognitive co-designer concurrently resolves multidimensional physical trade-offs.

In the era of open computing, RISC-V is the most prolific and open Instruction Set Architecture in history. The talk will introduce the history and the status of RISC-V including its applications and ecosystem around the world. The future of RISC-V will also be discussed.

Hand-crafted agentic AI workflows for hardware design automation are difficult to evolve, hard to adapt across heterogeneous EDA tool interfaces, and challenging to scale across workloads spanning RTL, verification, physical design, and manufacturing. Extending an agent from one flow to the next often resembles re-engineering rather than learning, limiting generalizability and maintainability.

This talk reframes agentic hardware design automation as a trainable, self-improving system. We present four complementary studies that demonstrate learning at different levels of the design automation stack: self-improving workflows that iteratively refine agent execution through experience and self-evolution; operator-level rule learning for formal verification that extracts reasoning traces from learned operator-level reasoning trees; autonomous log ingestion using question trees and gradient boosting to extract knowledge from diverse log formats; and Auto Research in the EDA Domain, a paper-grounded research harness that uses Monte Carlo Tree Search to explore candidate ideas and learn their value through iterative evaluation. Together, these methods show how agents can improve from experience, transfer across workflows, absorb knowledge from prior work, and reduce dependence on manual prompt engineering, pointing toward continuously improving hardware design automation systems.

Hand-crafted agentic AI workflows for hardware design automation are difficult to evolve, hard to adapt across heterogeneous EDA tool interfaces, and challenging to scale across workloads spanning RTL, verification, physical design, and manufacturing. Extending an agent from one flow to the next often resembles re-engineering rather than learning, limiting generalizability and maintainability.

This talk reframes agentic hardware design automation as a trainable, self-improving system. We present four complementary studies that demonstrate learning at different levels of the design automation stack: self-improving workflows that iteratively refine agent execution through experience and self-evolution; operator-level rule learning for formal verification that extracts reasoning traces from learned operator-level reasoning trees; autonomous log ingestion using question trees and gradient boosting to extract knowledge from diverse log formats; and Auto Research in the EDA Domain, a paper-grounded research harness that uses Monte Carlo Tree Search to explore candidate ideas and learn their value through iterative evaluation. Together, these methods show how agents can improve from experience, transfer across workflows, absorb knowledge from prior work, and reduce dependence on manual prompt engineering, pointing toward continuously improving hardware design automation systems.

AI is reshaping computing architectures across every level of integration, from chiplets within a package to accelerator clusters spanning entire data centers. At the center of this transformation lies the substrate, which is evolving from a passive carrier into a critical system-enabling platform. Advanced substrates support scale-in integration through chiplets, HBM, interposers, and panel-level packaging; scale-up architectures through CXL-enabled memory expansion and pooling; and scale-out AI fabrics enabled by UALink.

Looking ahead, substrates will also play a pivotal role in the deployment of co-packaged optics, providing the electrical, mechanical, thermal, and photonic integration platform required to overcome the bandwidth and energy limitations of copper interconnects. This talk explores how substrate innovations are enabling the next generation of AI infrastructure while addressing the challenges of signal integrity, power delivery, thermal management, reliability, manufacturability, and cost.

Agentic AI is beginning to transform electronic design automation from a collection of specialized tools into intelligent engineering systems capable of planning, executing, evaluating, and improving complex design and verification workflows. In this presentation, Cadence will share its technical perspective and vision for applying agentic AI across semiconductor design. The talk will examine the architectural foundations required for production-grade engineering agents, including deep integration with EDA tools, persistent design understanding, domain-specific reasoning, multi-agent orchestration, and closed-loop learning from simulation, formal analysis, coverage, and debug results. It will also discuss why model intelligence alone is insufficient and why trustworthy agents must continuously validate their decisions against deterministic engineering tools and measurable design outcomes. Practical examples will illustrate how agents can assist with design understanding, test planning, assertion and testbench generation, coverage closure, root-cause analysis, and iterative debugging. The presentation will conclude with Cadence's vision for a future in which engineers work collaboratively with specialized agents that automate repetitive tasks, preserve engineering intent, and accelerate the path from specification to verified silicon—while keeping engineers firmly in control of critical decisions.