Electronic Design Process Symposium

Silicon Integration Initiatives (Si2) is a member driven organization which provides collaborative technology and services to enable advanced semiconductor design integration, leading to industry-accepted standards. Si2 offers these standards, technology, and services to all interested organizations and individuals at a reasonable cost. Engineers from ~65 member companies collaborate on technology that leads to new standards for semiconductor design integration. Si2 OpenAccess and Compact Model Coalitions provide a virtuous cycle of value creation to their members. Si2 has new initiatives focusing on UPM, 3D multi-die, processed data & AI/ML. Deeper member engagement, shorter learning cycles, and agile concepts are needed so the velocity of new programs match the rate of industry change and deliver virtuous cycles of value creation to you.

When the technology nodes relentless advancing beyond 5nm, the EDA optimization for power-performance-area-cost (PPAC) is more and more challenging because of the increasing number and complexity of design rules, routability considerations, and strict pattern rules. Machine learning (ML) techniques can be leveraged to improve the productivity and efficiency for EDA Optimization, and even generate high quality solutions for EDA applications. In this talk, I will introduce interesting ML techniques for challenging EDA optimization problems in standard cell design, placement, and timing optimization areas. I will discuss the sequential model-based optimization, transformer model-based approach and reinforcement learning for EDA optimization. For the efficiency, the gradient descent-based optimization approach has been used widely for optimization in high dimensional spaces. Powered by deep learning frameworks and architectures, it can solve many EDA optimization problems efficiently. Finally, I will outline and explain the importance of integrating ML as well as GPU acceleration for EDA.

In the rapidly evolving landscape of Machine Learning (ML), there's a growing focus on enhancing efficiency for models, especially powerful vision models and Large Language Models (LLMs). While these models are revolutionizing how computers "see" and "understand", they come with substantial computational demands. Addressing this challenge, there's a noticeable trend towards sparsity - a method to trim non-essential components, making these models faster and more efficient. In this presentation, we'll not only discuss the transformative impact of vision models and LLMs but also the rising trend of ML inference sparsity support. Additionally, we'll survey and take an in-depth look at both commercial and academic accelerators tailored for sparsity. By the end, attendees will have a comprehensive understanding of current trends and the future trajectory of ML inference with sparsity support.

With the rapid advancements in AI/ML generating significant enthusiasm, there has been a growing interest in exploring their potential applications within the electronic design automation (EDA) industry. However, it is imperative to exercise caution and avoid indiscriminately applying AI/ML algorithms to every problem. Instead, it is required to consider the appropriateness of AI/ML algorithms with respect to the problem's scale, complexity, and data volume. Moreover, successful implementation often demands the customization and adaptation of these algorithms to effectively address the distinctive challenges presented by the EDA sector. This presentation delves into a selection of recent AI/ML use-cases developed by Keysight Technologies, specifically designed to tackle these challenges. The use-cases encompass a wide range of applications, including device modeling, high-speed channel analysis, and the 5G/6G network analysis. Furthermore, this talk provides a brief overview of the techniques employed in these use-cases, such as convolutional neural networks, Keysight artificial neural networks, and Bayesian optimization. Real-world examples and results are also presented to validate the effectiveness of these proposed approaches.

Generative AI models have gained large attention recently in many areas. In this presentation we will describe our application of Conditional Generative Adversarial Network (cGAN) models for high-speed system modelling and multi-physics power to thermal analysis. Unlike traditional discriminative simulation models, generative models attempt to model the joint distribution of the simulation input and output. When presented with unseen inputs or state condition within certain boundaries, cGAN can produce the correct results even though they were not in the training set. Digital twins are generative models with near real time inference speed that can represent the system performance. They allow us to dynamically optimize the system performance given a certain input condition. We will present two examples of such digital twins in high speed PAM4 SerDes and packaging power to thermal analysis.
The talk will be organized as follows. We will start with an introduction into generative model and GAN. We will describe the experimental setup and data collection procedures. The train models will be compared with real measured data or current multi-physics simulator. The talk will conclude with some of the key learnings we gained and future plans for cGAN engines.

VLSI physical design, the process that converts circuit schematics to manufacturable layouts in an automatic fashion, consists of many long-lasting and challenging problems that have been solved by sub-optimal algorithms over the decades. As the technology scaling advances, the sub-optimality becomes more severe and problematic. Machine learning (ML) is one of the promising solutions that help designers achieve the desired Power, Performance, and Area (PPA) goals. In this talk, we present our recent works on utilizing ML algorithms to improve various stages of the modern physical design flow. They span from partitioning, placement, routing, and timing optimization, where Reinforcement, Transformer, Adversarial, and Graph Learning are adopted. We also showcase our recent work recognized with the best paper award from the ACM Design Automation Conference in 2023.

Thermal mitigation of large complex 3DIC systems has been identified as a major challenge that limits the system performance and yield. The thermal problem is especially apparent in vertically stacked dies. In this talk, challenges and opportunities related to thermal modeling and simulation of heterogeneously integrated 3DICs will be discussed. Techniques leveraging ML-augmented multi-physics simulation will also be explored as a means to address the need for fast static/transient thermal simulations for thermal throttling and test applications.

High-performance workloads demand on-package integration of heterogeneous processing units, on-package memory, and communication infrastructure to meet the demands of the emerging compute landscape. Applications such as artificial intelligence, machine learning, data analytics, 5G, automotive, and high-performance computing are driving these demands to meet the needs of cloud computing, intelligent edge, and client computing infrastructure. On-package interconnects are a critical component to deliver the power-efficient performance with the right feature set in this evolving landscape.
UCIe is an open industry standard with a fully specified stack that comprehends plug-and-play interoperability of chiplets on a package; similar to the seamless interoperability on board with well-established and successful off-package interconnect standards such PCI Express, Universal Serial Bus (USB), and Compute Express Link (CXL). In this talk, we will discuss the usages and key metrics associated with different technology choices. We will also delve into the different layers as well as the software model along with the compliance and interoperability mechanisms.

Design-for-Test (DFT) is under double pressure already in 2D. On the one side, traditional quality measures are no longer sufficient. More parametric defects, increased susceptibility to aging, and the challenge of silent data corruption all require new solutions. On the other side, AI chips leading the way of pushing the limits of design sizes. Traditional test pattern delivery methods are no longer sufficient. To keep the costs in check, new DFT architectures are required. Unfortunately, 3D devices are of the same envelope pushing type in both quality requirements and total size, plus adding their own, new test requisites to the mix. In this talk, we'll discuss those and other DFT challenges, and explore possible paths forward for DFT for 3D devices.

AI for chip design and EDA has received tremendous interest from both academia and industry in recent years. It touches everything that chip designers care about, from PPA to cost/yield, turn-around-time, security, and so on. It is everywhere, in all levels of design abstractions, testing, verification, DFM, mask synthesis / ILT, and some aspects of analog/mixed-signal/RF designs as well. It has also been used to tweak the overall design flow and hyper-parameter tuning, but not yet all at once, e.g., generative AI from design specification to layout - correct by construction. In this talk, I will cover some recent advancement/breakthroughs in AI for chip design/EDA and share my perspectives.

Generative AI has taken the world by storm and is impacting numerous application areas ranging from music and art to engineering design and scientific discovery. In this talk, we will first present several examples of generative AI technology and deployment, such as knowledge-based approaches going back to Chef Watson and statistical approaches including large language models. Then we discuss desiderata and public policy around generative AI, including recent efforts in the U.S. federal government. Finally, we will detail a new approach to generative AI called information lattice learning that reifies many of the desiderata and policy objectives.

LLMs have emerged as powerful tools, revolutionizing various domains from natural language processing to content generation, but beneath their remarkable capabilities lie intricate challenges and perils that demand our attention.
While they offer convenience and productivity, we dissect how they can also be manipulated and weaponized by malicious actors, raising concerns about inherent biases, jailbreaking potential, security concerns, privacy issues, misinformation, deepfakes, cyber threats and their unsettling societal consequences. We explore how biases present in training data, historical injustices, and societal prejudices can be perpetuated and even amplified by these models, posing a significant threat to fairness, equity, and inclusivity.
This talk is aimed at raising awareness and engage the audience in a critical dialogue on these multifaceted challenges posed by LLMs. By understanding these challenges, we can collectively work towards harnessing the power of these models for the betterment of society while safeguarding against their unintended consequences.

In this talk, we propose an architecture that combines the advantages of centralized and decentralized federated learning schemes. In a centralized system, all participants are expected to contribute their datasets in advance, which is not always feasible given myriad privacy laws and security concerns. Each participant retains its dataset in a decentralized system while the training algorithm travels between the sites. We described the security risks and potential performance issues. We propose to overcome both the security and performance issues with a new Mixed-mode Cloud-based System.

Protecting silicon from attack is the next frontier in chip design. Our work on DARPA's AISS Program (Automatic Implementation of Secure Silicon) brought us together with some of the leading minds in the country to focus on addressing four semiconductor attack surfaces: Supply Chain, Reverse Engineering, Side Channel, and insertion of Malicious Hardware (i.e. hardware trojans). In this talk, we review common vulnerabilities in these areas along with security countermeasures that can be deployed by designers to mitigate such attacks.

Silent data corruptions (SDC) in hardware impact computational integrity for large-scale applications. Sources of corruptions include datapath dependencies, temperature variance, and age among other silicon factors. These errors do not leave any record or trace in system logs. As a result, silent errors stay undetected within workloads, and can propagate across the stack to the applications. Silent errors can result in data loss and can require months of debug engineering time. In our large-scale infrastructure, we have run a vast library of silent error test scenarios across hundreds of thousands of machines in our fleet. This has resulted in hundreds of CPUs detected for these errors, showing that SDCs are a systemic issue across device generations. Based on this experience, we determine that reducing silent data corruption requires not only hardware resiliency and production detection mechanisms, but also robust fault-tolerant software architectures.

In advanced packaging, as newer forms of interconnects emerge to meet the demand for high density and high performance, interconnect reliability is becoming more complex and more critical. Finer pitch interconnects in advanced packaging are more susceptible to failures due to electromigration, interfacial reactions etc. Wafer level packaging, 3DIC and Cu direct bonding, and other advanced packaging technologies, present new considerations in interconnect reliability. At the same time, the growing adoption of heterogeneous integration leads to increased diversity of interconnects (with different geometries, materials, and interfaces) in the same package, with complex (and often interactive) reliability failure modes and mechanisms.
As electronic products become more pervasive in application, interconnect reliability must be considered holistically with regard to environmental conditions, from thermal, mechanical, and thermomechanical, to electrical and electrochemical. High frequency applications demand considerations of interconnect materials for signal integrity. High thermal density and high current density can have increased impact on interconnect reliability. These considerations will impact reliability engineering for semiconductor devices, from design for reliability, to accelerated testing and analysis.
Understanding of the failure mechanisms for different interconnect materials at various levels (wafer, chip, package, and system) of the semiconductor package is of great importance to interconnect reliability in advanced packaging and heterogeneous integration.

The growing challenge of addressing Silent Data Corruption necessitates the need for increased resiliency of hardware components, with enhanced RAS capabilities for HPC and mission critical use cases. With technology scaling, integration, increase threat surface, multi-die packages and safety critical applications, we need to consider mitigations in design, architecture, test and employ best practices throughout the hardware device lifecycle. In order to meet these challenges, Silicon Lifecycle Management (SLM) solutions will be critical to improve silicon health and operational metrics. Silicon Lifecycle Management IP enable performance and resiliency needs for high computation and also provide the monitoring and detection capabilities needed to greatly enhance manufacturing quality and product integrity in the field.