Our Cast
Chuck Alpert
Cadence
Charles (Chuck) Alpert is Cadence's AI Fellow and drives cross-functional Agentic AI solutions throughout Cadence's software stack. Prior to this, has lead various pioneering teams in digital implementation, including Global Routing, Clock Tree Synthesis, Genus Synthesis, and Cerebrus AI. Charles has published over 100 papers and received over 100 patents in the EDA space. He is a Cadence Master inventor. He has served as Deputy-Editor-in-Chief for IEEE Transactions on Computer-Aided Design, chaired the IEEE/ACM Design Automation Conference, and earned IEEE Fellow. He received a B.S. and B.A. Degree from Stanford University and a Ph.D. in Computer Science from UCLA.
Matt Bromley
Siemens
Matt Bromley is responsible for product strategy and technology for the Electronic Board Systems Group. He has been a part of the EDA industry for over 30 years, having worked for both at start-ups and large multi-national companies, including Cadence Design Systems, and currently Siemens. He has held a variety of technical roles in engineering and management. Matt is passionate about bringing the most capable solutions to solve EDA challenges for our customers. Matt is currently responsible for the product strategy for the Electronic Board Systems' products. Matt has a Masters in Software Engineering from the University of York, UK.
Norman Chang
Synopsys
Norman Chang co-founded Apache Design Solutions in February 2001 and currently serves as Ansys Fellow and Chief Technologist at Electronics, Semiconductor, and Optics BU, ANSYS, part of Synopsys. He is also currently leading AI/ML and security initiatives at ANSYS. Dr. Chang received his Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds 34 patents and has co-authored over 60 IEEE papers and a popular book on ”Interconnect Analysis and Synthesis” by Wiley&Interscience at 2000. Dr. Chang is an IEEE Fellow for his contribution on ”Leadership and contributions to the physical-level sign-off of Electronic Design Automation for SoC/3DIC”. He is also a recipient of 2024 ”Distinguished Entrepreneur of the Year” Award from Chinese Institute of Engineers (CIE). He also actively engages in industry committees such as IEEE EDPS (Electronic Design Process Symposium) and SI2.
Preeth Chengapappa
Microsoft
Preeth Chengappa leads GenAI-focused industry engagements across Physics &
Semiconductors at Microsoft for the newly launched Discovery platform, which brings enterprise- grade agentic capabilities to science and engineering. Preeth has deep industry expertise in the
semiconductor industry, working across commercial and government entities, and represents Microsoft on the US CHIPS Act, EU and other nations' equivalents for semiconductors, secure cloud, and GenAI. In 2011, Preeth co-founded SiCAD, a startup that built the first cloud-based chip design platform leveraging industry standard tools. He has held engineering, product, and business development leadership roles in large enterprises and startups. Preeth graduated from NITK, India, with a degree in Chemical Engineering.
Chris Cheng
Hewlett-Packard Enterprise
Chris Cheng is a Distinguished Technologist in Primary Storage Division of Hewlett-Packard Enterprise. He is responsible for managing hardware machine learning development and high-speed design within the Storage Division. He also held senior engineering positions in Sun Microsystems where he developed the original GTL system bus with Bill Gunning. He was a Principal Engineer in Intel where he led high speed processor bus design team. He was the first hardware engineer in 3PAR and guided their high-speed design effort until it was acquired by Hewlett Packard.
Patrick Groeneveld
AMD
Patrick is Senior Fellow at AMD and adjunct lecturer in Stanford University's Department of Electrical Engineering. With an extensive career in Electronic Design Automation, he has held roles at both Cadence and Synopsys and served as Chief Technologist at Magma Design Automation, where he contributed to the development of a pioneering RTL-to-GDS2 synthesis tool. Patrick has also worked with AI hardware startups and held a Full Professorship in Electrical Engineering at Eindhoven University. He is the Finance Chair on the Executive Committee of the Design Automation Conference. Patrick earned his MSc and PhD degrees from Delft University of Technology in the Netherlands.
Bin Hu
UIUC
Bin Hu received the B.Sc. in Theoretical and Applied Mechanics from the University of Science and Technology of China in 2008, and received the M.S. in Computational Mechanics from Carnegie Mellon University in 2010. He received the Ph.D. in Aerospace Engineering and Mechanics at the University of Minnesota in 2016. Between July 2016 and July 2018, he was a postdoctoral researcher in the Wisconsin Institute for Discovery at the University of Wisconsin-Madison. He is currently an assistant professor in the Department of Electrical and Computer Engineering at the University of Illinois Urbana-Champaign and affiliated with the Coordinated Science Laboratory. His research develops foundational connections between AI/ML and core engineering domains such as control, analog IC design, computer architecture, and mechanical systems. He received the NSF CAREER Award and the Amazon Research Award in 2021, and the O. Hugo Schuck Best Paper Award in 2024.
Alex Petr
Keysight
Alexander Petr, Senior Director for Keysight EDA. In his current role Alex manages Keysight's Portfolio for RF-microwave, Power Electronics, Device Modeling and drives Keysight EDA AI/ML initiatives.
Alex earned his M.Sc. in nano-electronics from the Technical University of Dresden (TU-Dresden), Germany. Throughout his career, he has worked across three continents in diverse roles spanning the entire analog/mixed-signal and RF design supply chain. He is recognized as an expert in foundry technologies, metrology and measurement, PDK and design support, as well as EDA software development. In recent years, Alex has led AI/ML initiatives at Keysight to advance the next generation of AI-enabled circuit design, inverse design synthesis, and LLM-based solutions. He serves as the principal investigator for the Natcast AIDRFIC program, dedicated to commercializing a new generation of AI-enabled RFIC design tools that are fully qualified and certified by leading foundries for both silicon and III-V technologies.
Mark Ren
Nvidia
Haoxing (Mark) Ren is the Director of Design Automation Research at NVIDIA, focusing on leveraging machine learning and GPU-accelerated tools to enhance chip design quality and productivity. He has over 25 years of industrial EDA research and development experience at IBM and NVIDIA. He holds over thirty patents and has co-authored over 100 papers and books, including a book on ML for EDA and several book chapters in EDA. He received several prestigious awards for his work, including the IBM Corporate Award and best paper awards at ISPD, DAC, TCAD, MLCAD and LAD. He serves in the organization and steering committees of international conferences such as ICCAD and ISPD and as the conference chair at ICLAD. He holds Bachelor's and Master's degrees from Shanghai Jiao Tong University and Rensselaer Polytechnic Institute, respectively, and earned his PhD from the University of Texas at Austin. He is a Fellow of the IEEE.
Sandeep Sane
Lightmatter
Sandeep Sane is Senior Director and Head of Packaging at Lightmatter, where he leads advanced packaging development for the Passage and LASER product lines. Previously, he was a Principal Engineer at Intel, contributing to silicon-package co-design and co-inventing the widely adopted EMIB packaging technology. He holds over 20 patents and has authored numerous technical publications. Earlier in his career, he worked at IBM Microelectronics. He earned his Ph.D. and M.S. from Caltech and his B.S. from IIT Bombay
Naresh Sehgal
Secure the Cloud
Naresh K. Sehgal is a Cloud and Security consultant. Most recently, he was the Senior Vice President of Cloud Engineering and Chief Information Security Officer (CISO) at NovaSignal, a medical Startup. Before that, he was at Intel for more than 31 years in various engineering and management roles. Naresh has earned a B.E. (Electrical Engineering) from Punjab Engineering College, an M.S., and a Ph.D. from Syracuse University in Computer Engineering. Naresh has taught Cloud Computing at Santa Clara University, where he also earned an MBA.
Kexun Zhang
ChipAgents.ai
Kexun Zhang is the Head of Research at ChipAgents.ai. He has authored numerous publications on artificial intelligence, with a focus on AI agents. Kexun has developed multiple agents that achieved top-1 performance on SWE-Bench, a leading benchmark for coding agents, and led ChipAgents' efforts to achieve state-of-the-art results on VerilogEval, a widely adopted benchmark for RTL generation.